| CMSIS-Pack Version 1.3.1 Delivery Mechanism for Software Packs

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/package/devices/family element

# /package/devices/family

Define properties that are in common to all devices of a family. These properties are inherited by subgroups or elements. This is a mechanism of granulation to reduce redundancy. Multiple <family> groups can be defined.

Example

<devices>
...
<family Dfamily="STM32F2" Dvendor="STMicroelectronics:13">
<processor .../>
<debugconfig .../>
<debugvars .../>
<sequences .../>
<compile .../>
<memory .../>
<algorithm .../>
<book .../>
<description> Write texte here </description>
<environment> ... </environment>
<feature .../>
<debugport .../>
<debug .../>
<trace .../>
<subfamily Dsubfamily="...">
...
<device Dname="...">
...
</device>
...
</subfamily>
...
</family>
...
</devices>

Parents | Element Chain
--- | ---
devices | /package/devices
Attributes | Description | Type | Use
Dfamily | Name of the device family. | xs:string | required
Dvendor | Device vendor name. Use predefined values as listed in the table Device Vendor. | DeviceVendorEnum | required
Child Elements | Description | Type | Occurrence
processor | List all processors that are in common to devices of the family. | ProcessorType | 0..*
compile | Specify compile or translate options that are relevant to all devices of the family. | CompileType | 0..*
debugconfig | Specify default settings for the debug connection relevant to all devices of the family. | DebugConfigType | 0..1
debugvars | Define global debug access variables for settings relevant to all devices of the family unless replaced by debugvars on subfamily, device or variant level | DebugVarsType | 0..1
sequences | Describe debug access sequences relevant to all devices of the family. | SequencesType | 0..1
debugport | Describe a debug port relevant to all devices of the family. | DebugPortType | 0..*
debug | Specify debug options that are relevant to all devices of the family. | DebugType | 0..*
trace | Specify trace options that are relevant to all devices of the family. | TraceType | 0..*
memory | Specify memory areas that are available for all devices of the family. | MemoryType | 0..*
algorithm | Specify Flash programming algorithms that are suitable for all devices. | AlgorithmType | 0..*
book | Specify documents that are relevant for all devices of a family. | BookType | 0..*
description | Describe the device family. | DescriptionType | 0..*
environment | Specify tool specific settings. | EnvironmentType | 0..*
feature | Specify features that are available in all members of the device family. | FeatureType | 0..*
subfamily | A optional sub-family that is used to group devices. | group | 0..*
device | Individual devices that belong to the device family. | DeviceType | 0..*

# /package/devices/family/subfamily

Define properties that are in common to all devices of a subfamily. This is another mechanism of granulation to reduce redundancy. These properties are inherited by subgroups or elements. Multiple <subfamily> groups can be defined.

Example

<family Dfamily="STM32F2" Dvendor="STMicroelectronics:13">
...
<subfamily Dsubfamily="...">
<processor .../>
<debugconfig .../>
<debugvars .../>
<sequences .../>
<compile .../>
<memory .../>
<algorithm .../>
<book .../>
<description> Write texte here </description>
<feature .../>
<debugport .../>
<debug .../>
<trace .../>
<device Dname="...">
...
</device>
</subfamily>
<subfamily Dsubfamily="STM32F2xx">
...
</subfamily>
</family>

Parents | Element Chain
--- | ---
family | /package/devices/family
Attributes | Description | Type | Use
Dfamily | Name of the device family. | xs:string | required
Child Elements | Description | Type | Occurrence
processor | Specify processors that are available in all devices of the sub-family. | ProcessorType | 0..*
compile | Specify compile or translate options that are relevant to all devices of the sub-family. | CompileType | 0..*
debugconfig | Specify default settings for the debug connection relevant to all devices of the sub-family. | DebugConfigType | 0..1
debugvars | Define global debug access variables for user-defined settings relevant to all devices of the sub-family. | DebugVarsType | 0..1
sequences | Describe debug access sequences relevant to all devices of the sub-family. | SequencesType | 0..1
debugport | Describe a debug port relevant to all devices of the sub-family. | DebugPortType | 0..*
debug | Specify debug options that are relevant to all devices of the sub-family. | DebugType | 0..*
trace | Specify trace options that are relevant to all devices of the sub-family. | TraceType | 0..*
memory | Specify memory areas that are available in all device of the sub-family. | MemoryType | 0..*
algorithm | Specify Flash programming algorithms that can be used by all device of the sub-family. | AlgorithmType | 0..*
book | Specify documents relevant for all device of the sub-family. | BookType | 0..*
description | Description of the device family. | DescriptionType | 0..*
feature | Specify features available in devices of the sub-family. | FeatureType | 0..*
device | List individual devices that belong to the device sub-family. | DeviceType | 0..*

# /package/devices/family/../device

Define properties that are specific to a device. Properties defined on upper levels get inherited, unless they can be overwritten. Multiple <device> elements can be defined.

Example

<subFamily DsubFamily="STM32F405">
...
<device Dname="STM32F405OE">
<memory id="IROM1" start="0x08000000" size="0x80000" startup="1" default="1"/>
<algorithm name="Flash\STM32F4xx_1024.flm" start="0x08000000" size="0x80000" default="1"/>
<feature type="IOs" n="72" name="Input and Output Ports"/>
</device>
<device Dname="STM32F405OG">
<memory id="IROM1" start="0x08000000" size="0x100000" startup="1" default="1"/>
<algorithm name="Flash\STM32F4xx_1024.flm" start="0x08000000" size="0x100000" default="1"/>
<feature type="IOs" n="72" name="Input and Output Ports"/>
</device>
...
</subfamily>

Parents | Element Chain
--- | ---
family | /package/devices/family
subfamily | /package/devices/family/subfamily
Attributes | Description | Type | Use
Dname | Specifies the name of the device. | xs:string | required
Child Elements | Description | Type | Occurrence
processor | Specify processors that are specific to this device. | ProcessorType | 0..*
compile | Specify compile or translate options specific to this device. | CompileType | 0..*
debugconfig | Specify default settings for the debug connection specific to this device. | DebugConfigType | 0..1
debugvars | Define debug access variables for user-defined settings specific to this device. | DebugVarsType | 0..1
sequences | Describe debug access sequences specific to this device. | SequencesType | 0..1
debugport | Describe a debug port specific to this device. | DebugPortType | 0..*
debug | Specify debug options specific to this device. | DebugType | 0..*
trace | Specify trace options specific to this device. | TraceType | 0..*
memory | Specify memory areas that specific to this device. | MemoryType | 0..*
algorithm | Specify Flash programming algorithms that can be used by this device. | AlgorithmType | 0..*
book | Specify documents specific to this device. | BookType | 0..*
description | Description specific to this device. | DescriptionType | 0..*
feature | Specify features specific to this device. | FeatureType | 0..*
variant | Complex element specifying a variant of a device. | VariantType | 0..*

# /package/devices/family/.../algorithm

Specify Flash programming algorithms with the address range and its size. An algorithm with <default> set to true gets configured automatically to the download options of the project. Algorithms can be defined on various levels. Multiple <algorithm> elements are possible.

Example

<family Dfamily="STM32F4" Dvendor="STMicroelectronics:13">
...
<algorithm name="Flash\STM32F2xx_512.flm" start=0x08000000 size=0x10000 default="1"/> <!-- valid for all devices of the family -->
<subFamily DsubFamily="STM32F405">
<algorithm name="Flash\STM32F2xx_1024.flm" start=0x08000000 size=0x20000 default="1"/> <!-- valid for all devices of a subFamily -->
<device Dname="STM32F405OE">
<algorithm name="Flash\STM32F2xx_2048.flm" start=0x08000000 size=0x40000 default="1"/> <!-- finally, this is the default for the device -->
</device>
...
</family>

Parents | Element Chain
--- | ---
family | /package/devices/family
subfamily | /package/devices/family/subfamily
device | /package/devices/family/../device
Attributes | Description | Type | Use
Pname | Processor identifier. This attribute is mandatory for devices that embed multiple processors. | xs:string | optional
name | Flash Programming Algorithm file including the path, which is relative to the root folder of the Software Pack. | xs:string | required
start | Base address for the Flash programming algorithm. | NonNegativeInteger | required
size | Size covered by the Flash programming algorithm. End address = start + size - 1 | NonNegativeInteger | required
RAMstart | Base address for the RAM where the Flash programming algorithm will be executed from. If specified, the memory element does not require a `default` attribute. | NonNegativeInteger | optional
RAMsize | Maximum size of RAM available for the execution of the Flash programming algorithm. End address = start + size - 1 is used for the Stack. If specified, the memory element does not require a `default` attribute. | NonNegativeInteger | optional
default | If true, then this is the default Flash programming algorithm that gets configured in a project. If not specified or set to false, then the Flash programming algorithm can be configured on a lower level. However, the Flash programming algorithm of a project can be changed manually at any time during development. | xs:boolean | optional

# /package/devices/family/.../book

Specifies documents related to a device. Books can be entered on various levels. The book element contains the location, filename, and extension of the file. The title is used for display purposes.

Example

<family Dfamily="STM32F4" Dvendor="STMicroelectronics:13">
...
<book name="Documents\STM32F40x_DS.PDF" title="STM32F40x Data Sheet"/> <!-- valid for all devices of the family -->
<subFamily DsubFamily="STM32F405">
<book name="Documents\STM32F4xx_RM.pdf" title="STM32F4 Series Reference Manual"/> <!-- valid for all devices of a subFamily -->
<device Dname="STM32F405OE">
<book name="Documents\STM32F405OE_DS.PDF" title="STM32F405OE - Data Sheet"/> <!-- valid for this device; Inherits all above -->
</device>
...
</family>

Parents | Element Chain
--- | ---
family | /package/devices/family
subfamily | /package/devices/family/subfamily
device | /package/devices/family/../device
Attributes | Description | Type | Use
Pname | Processor identifier. This attribute is mandatory for devices that embed multiple processors. | xs:string | optional
name | File name of the document including the extension. The document path is relative to the package base folder. Directory/file names are case-sensitive. | xs:string | required
title | Book title. Can be used for being displayed in various environments. | xs:string | required

# /package/devices/family/.../compile

Specify header files and preprocessor defines for programming. This element can occur on various levels. Multiple elements are allowed. The last occurrence in the hierarchy determines the actual define.

Note
  - In the example below, the device STM32F407IG will have a define `STM32F407IG`. Previous defines are overridden.
  - It is good practice to add both attributes (`header` and `define`) in the attributes list of the `compile` element together. This clarifies the relationship between header file and define.

Example

<family Dfamily="STM32F4" Dvendor="STMicroelectronics:13">
...
<compile header="Device\Include\stm32f4xx.h"/>
<subFamily DsubFamily="STM32F407">
...
<compile header="Device\Include\stm32f4xx.h" define="STM32F40XX"/>
<device Dname="STM32F407IG">
<compile header="Device\Include\stm32f4xx.h" define="STM32F407IG"/>
</device>
</subfamily>
</family>

Parents | Element Chain
--- | ---
family | /package/devices/family
subfamily | /package/devices/family/subfamily
device | /package/devices/family/../device
Attributes | Description | Type | Use
Pname | Processor identifier. This attribute is mandatory for devices that embed multiple processors. | xs:string | optional
header | C-header file with path relative to the installation. | xs:string | optional
define | C-file name with device specific preprocessor defines. The path is relative to the installation. | xs:string | optional

# /package/devices/family/.../description

Brief description of the element. Can occur on various levels. Should only contain the unique features of the device. Number of bullet points should not exceed ten. To create a detailed feature list use the /package/devices/family/.../feature instead.

Example

<package>
<devices>
<family Dfamily="STM32F2" Dvendor="STMicroelectronics:13">
<description>
STM32F2 devices are designed for medical, industrial and consumer
applications and provide rich connectivity peripherals.
- At 120 MHz CPU clock: 150 DMIPS executing from Flash memory
- ART Accelerator for low-power Flash execution (175 µA/MHz @ 120 MHz)
- Flexible Memory Controller supports Compact Flash, SRAM, PSRAM, NOR and NAND
</description>
</family>
</devices>
</package>

Parents | Element Chain
--- | ---
family | /package/devices/family
subfamily | /package/devices/family/subfamily
device | /package/devices/family/../device
Attributes | Description | Type | Use
Pname | Processor Identifier. This attribute is mandatory for devices that embed multiple processors. | xs:string | optional

# /package/devices/family/.../environment

Tool-specific elements for a device.

Can occur on various levels.

Contains information that is specific for a development tool identified by the name attribute. The structure of the element is not specified in the schema file which gives the development tool full control of the element usage.

Example

<package>
<devices>
<family Dfamily="MySeries" Dvendor="Generic:5">
...
<environment name="MyConfigTool">
<file>MyConfigFile.cfg</file>
<control>MyControlString</control>
...
</environment>
...
</family>
</devices>
</package>
<package>
<devices>
<family Dfamily="XMC1000 Series" Dvendor="Infineon:7">
...
<environment name="uv" Pname="M0">
<CMisc>--C99</CMisc>
...
</environment>
...
</family>
</devices>
</package>

Parents | Element Chain
--- | ---
family | /package/devices/family
subfamily | /package/devices/family/subfamily
device | /package/devices/family/../device
Attributes | Description | Type | Use
name | Name of the development tool (e.g. "uv" for uVision) | xs:string | required
Pname | Identifies the processor the setting belongs to. | xs:string | optional
Child Elements | Description | Type | Occurrence
any | Any element that is available for the specified development tool. For uVision, the following elements are available: <CMisc>, <AMisc>, <LMisc>, <preBuild1>, <preBuild2>, <preRun1>, <preRun2>, <postBuild1>, <postBuild2>, <postRun1>, <postRun>. | xs:anyAttribute | 0..*

# /package/devices/family/.../feature

This element specifies the peripherals that devices can have. Many device feature types are already predefined, such as timers, converters, Ethernet, USB, etc (for a complete list refer to table Device Feature Types). Features can be defined on various levels. Inner elements supersede outer elements.

Example

<package>
<devices>
<family Dfamily="STM32F4" Dvendor="STMicroelectronics:13">
...
<!-- Features that are in common to this device family. -->
<feature type="TimerOther" n="1" name="Independent Watchdog Timer"/>
<feature type="TimerOther" n="1" name="Window Watchdog Timer"/> <!-- The same feature type can be specified multiple times -->
<feature type="Other" n="1" name="Temperature Sensor"/>
<feature type="CoreOther" n="1" name="96-bit Unique Identifier"/>
<feature type="CoreOther" n="1" name="CRC Calculation Unit"/>
<feature type="DMA" n="16" name="General Purpose DMA with Centralized FIFO and Burst Support"/>
<feature type="PowerOther" n="1" name="POR, PDR, PVD, and BOR"/>
<feature type="XTAL" n="4000000" m="26000000" name="Crystal Oscillator"/>
<feature type="IntRC" n="16000000" name="Internal Factory-Trimmed RC"/>
<feature type="IntRC" n="32000" name="Internal RC with Calibration"/>
<feature type="RTC" n="32000" name="RTC with 32 kHz calibrated Oscillator and Battery Backup"/>
<feature type="PowerMode" n="3" name="Run, Stop, Standby"/>
<feature type="Temp" n="-40" m="85"/>
<feature type="Temp" n="-40" m="105"/>
<feature type="Timer" n="4" m="16" name="General Purpose Timer"/>
...
<subFamily DsubFamily="STM32F407">
<!-- Features that are in common to this subfamily. -->
<feature type="IOs" n="36"/> <!-- adds new feature to subfamily -->
<feature type="Timer" n="7" m="32" name="General Purpose Timer"/> <!-- overrides settings from <family> -->
<device Dname="STM32F407IE">
<!-- Feature specific to this device. All above features are inherited. -->
<feature type="QFP" n="176" name="LQFP 176 24x24x1.4"/>
</device>
</subfamily>
</family>
</devices>
</package>

Parents | Element Chain
--- | ---
family | /package/devices/family
subfamily | /package/devices/family/subfamily
device | /package/devices/family/../device
Attributes | Description | Type | Use
Pname | Processor Identifier. This attribute is mandatory for devices that embed multiple processors. | xs:string | optional
type | A feature (peripheral), such as CAN, DMA, I/O, LCD, etc. Predefined values must be used as listed in the table Device Feature Types. | DeviceFeatureTypeEnum | required
n | Depends on the element type. Check table Device Feature Types. | xs:decimal | optional
m | Depends on the elemen type. Check table Device Feature Types. | xs:decimal | optional
name | Descriptive name of the feature. For example, "16-bit down counting timer". If omitted, the Default Name is used as described in the table Device Feature Types. | xs:string | optional

Table: Device Feature Types

The table lists predefined device features (peripherals).

Note
  The attribute name of the element /package/devices/family/.../feature is a descriptive text for a feature. If name is omitted, then the Default Name is used.

type= | n= | m= | Default Name | Example | Example shown as
--- | --- | --- | --- | --- | ---
NVIC | Number of NVIC Interrupts | N/A | NVIC | <feature type="NVIC" n="120" name="NVIC"/> | NVIC with 120 interrupt sources
DMA | Number of DMA Channels | N/A | DMA | <feature type="DMA" n="16" name="High-Speed DMA"/> | 16-channel High-Speed DMA
Crypto | Bitwidth, given as decimal Number (see example) | N/A | Cryptographic Engine | <feature type="Crypto" n="128.256" name="HW accelerated AES Encryption Engine"/> | 128/256-bit HW accelerated AES Encryption Engine
RNG | Number of RNGs | N/A | Random Number Generator | <feature type="RNG" name="True Random Number Generator"/> | True Random Number Generator
CoreOther | Number of Features | N/A | Other Core Feature | <feature type="CoreOther" n=1 name="96-bit Unique Identifier"/> | 1 x 96-bit Unique Identifier
Memory | Number of Bytes | N/A | Memory | <feature type="Memory" n="128" name="EEPROM"/> | 128 byte EEPROM
MemoryOther | Number of Memories | N/A | Other Memory Type | <feature type="MemoryOther" n="1" name="1 kB MRAM"/> | 1 x 1 kB MRAM
ExtBus | Bitwidth of Bus Interface | N/A | External Bus Interface | <feature type="ExtBus" n="16" name="External Bus Interface for SRAM Communication"/> | 16-bit External Bus Interface for SRAM Communication
XTAL | Minimum Frequency in Hz | Maximum Frequency in Hz | External Crystal Oscillator | <feature type="XTAL" n="4000000" m="25000000" name="External Crystal Oscillator"/> | 4 MHz .. 25 MHz External Crystal Oscillator
IntRC | Minimum Frequency in Hz | Maximum Frequency in Hz | Internal RC Oscillator | <feature type="IntRC" n="16000000" name="Internal RC Oscillator with +/- 1% accuracy"/> | 16 MHz Internal RC Oscillator with +/- 1% accuracy
PLL | Number of PLLs | N/A | PLL | <feature type="PLL" n="3" name="Internal PLL"/> | 3 Internal PLL
RTC | RTC Frequency | N/A | RTC | <feature type="RTC" n="32000" name="Internal RTC"/> | 32 kHz Internal RTC
ClockOther | Number of Peripherals | N/A | Other Clock Peripheral | <feature type="ClockOther" name="My special clock feature"/> | My special clock feature
PowerMode | Number of Power Modes | N/A | Power Modes | <feature type="Mode" n="3" name="Run, Sleep, Deep-Sleep"/> | 3 Power Modes: Run, Sleep, Deep-Sleep
VCC | Minimum Supply Voltage | Maximum Supply Voltage | Operating Voltage | <feature type="VCC" n="1.8" m="3.6"/> | 1.8 V .. 3.6 V
Consumption | Minimum Power Consumption | Typical Power Consumption | Power Consumption | <feature type="Consumption" n="0.00004" m="0.002" name="Ultra-Low Power Consumption"/> | 40 uW/MHz .. 2 mW/MHz Ultra-Low Power Consumption
PowerOther | Number of Features | N/A | Other Power Feature | <feature type="PowerOther" n="1" name="POR"/> | 1 x POR
BGA | Number of Balls | N/A | BGA | <feature type="BGA" n="256" name="Plastic Ball Grid Array"/> | 256-ball Plastic Ball Grid Array
CSP | Number of Leads | N/A | CSP | <feature type="CSP" n="28" name="Wafer-Level Chip-Scale Package"/> | 28-ball Wafer-Level Chip-Scale Package
PLCC | Number of Leads | N/A | PLCC | <feature type="PLCC" n="20" name="PLCC Package"/> | 20-lead PLCC Package
QFN | Number of Leads | N/A | QFN | <feature type="QFN" n="33" name="QFN Package"/> | 33-pad QFN Package
QFP | Number of Leads | N/A | QFP | <feature type="QFP" n="128" name="Low-Profile QFP Package"/> | 128-lead Low-Profile QFP Package
SOP | Number of Leads | N/A | SOP | <feature type="SOP" n="16" name="SSOP Package"/> | 16-lead SSOP Package
DIP | Number of Leads | N/A | SOP | <feature type="DIP" n="16" name="Dual In-Line Package"/> | 16-lead Dual In-Line Package
PackageOther | Number of Pins | N/A | Other Package Type | <feature type="PackageOther" n="44" name="My other Package"/> | 44-contacts My other Package
IOs | Number of I/Os | N/A | Inputs/Outputs | <feature type="IOs" n="112" name="General Purpose I/Os, 5V tolerant"/> | 112 General Purpose I/Os, 5V tolerant
ExtInt | Number of External Interrupts | N/A | External Interrupts | <feature type="ExtInt" n="12"/> | 12 External Interrupts
Temp | Minimum Operating Temperature | Maximum Operating Temperature | Operating Temperature Range | <feature type="Temp" n="-40" m="105" name="Extended Operating Temperature Range"/> | -40 °C .. +105 °C Extended Operating Temperature Range
ADC | Number of Channels | Resolution in Bit | ADC | <feature type="ADC" n="5" m="12" name="High-Performance ADC"/> | 5-channel x 12-bit High-Performance ADC
DAC | Number of Channels | Resolution in Bit | DAC | <feature type="DAC" n="2" m="10"/> | 2 x 12-bit DAC
TempSens | Number of Sensors | N/A | Temperature Sensor | <feature type="TempSens" n="1"/> | 1 x Temperature Sensor
AnalogOther | Number of Features | N/A | Other Analog Peripheral | <feature type="AnalogOther" n="1" name="My Analog"/> | 1 x My Analog
Timer | Number of Channels | Resolution in Bit | Timer/Counter Module | <feature type="Timer" n="2" m="32" name="Timer Module with Quadrature Encoding"/> | 2 x 32-bit Timer Module with Quadrature Encoding
PWM | Number of Channels | Resolution in Bit | PWM | <feature type="PWM" n="2" m="16" name="Pulse Width Modulation"/> | 2 x 16-bit Pulse Width Modulation
WDT | Number of Watchdogs | N/A | Watchdog | <feature type="WDT" n="1"/> | 1 x Watchdog Timer
TimerOther | Number of Features | N/A | Other Timer Peripheral | <feature type="TimerOther" n="1" name="Quadrature En-/Decoder"/> | 1 x Quadrature En-/Decoder
MPSerial | Number of Serial Peripherals | N/A | Multi-Purpose Serial Peripheral | <feature type="MPSerial" n="4" name="Multi-Purpose Serial Interface Module: I2C, I2S, SPI, UART"/> | 4 x Multi-Purpose Serial Interface Module: I2C, I2S, SPI, UART
CAN | Number of CAN Interfaces | N/A | CAN | <feature type="CAN" n="2" name="CAN 2.0b Controller"/> | 2 x CAN 2.0b Controller
Ethernet | Number of Ethernet Interfaces | Data Rate in Bit/s | Ethernet | <feature type="ETH" n="1" m="10000000" name="Integrated Ethernet MAC with PHY"/> | 1 x 10 Mbit/s Integrated Ethernet MAC with PHY
I2C | Number of I2C Interfaces | N/A | I2C | <feature type="I2C" n="2"name="Low-Power I2C"/> | 2 x Low-Power I2C
I2S | Number of I2S Interfaces | N/A | I2S | <feature type="I2S" n="3"/> | 3 x I2S
LIN | Number of LIN Interfaces | N/A | LIN | <feature type="LIN" n="4"/> | 4 x LIN
SDIO | Number of SDIO Interfaces | Bitwidth of SDIO Interface | SDIO | <feature type="SDIO" n="1" m="4" name="SDIO Interface"/> | 1 x 4-bit SDIO Interface
SPI | Number of SPI Interfaces | Data Rate in Bit/s | SPI | <feature type="SPI" n="2" m="20000000" name="SPI Interface"/> | 2 x 20 Mbit/s SPI Interface
UART | Number of UART Interfaces | Data Rate in Bit/s | UART | <feature type="UART" n="4" m="3000000" name="High-Speed UART Interface"/> | 4 x 3 Mbit/s High-Speed UART Interface
USART | Number of USART Interfaces | Data Rate in Bit/s | USART | <feature type="USART" n="2" m="1000000" name="High-Speed USART Interface"/> | 2 x 1 Mbit/s High-Speed USART Interface
USBD | Number of USB Dvice Interfaces | N/A | USB Device | <feature type="USBD" n="2" name="Full-Speed USB Device"/> | 2 x Full-Speed USB Device
USBH | Number of USB Host Interfaces | N/A | USB Host | <feature type="USBH" n="2" name="High-Speed USB Host"/> | 2 x High-Speed USB Host
USBOTG | Number of USB OTG Interfaces | N/A | USB OTG | <feature type="USBOTG" n="1" name="High-Speed USB OTG with PHY"/> | 1 x High-Speed USB OTG with PHY
ComOther | Number of other Communication Peripherals | N/A | Other Communication Peripheral | <feature type="ComOther" n="1" name="ZigBee"/> | 1 x ZigBee
Camera | Number of Camera Interface | Resolution in Bit | Camera Interface | <feature type="Camera" n="1" m="8" name="Digital Camera Interface"/> | 1 x 8-bit Digital Camera Interface
GLCD | Number of Graphic LCD Controller | Maximum Resolution as a decimal number (see example) | Graphic LCD Controller | <feature type="GLCD" n="1" m="320.240" name="TFT LCD Controller"/> | 1 x 320 x 480 pixel TFT LCD Controller
LCD | Number of Segment LCD Controller | Com.Seg as a decimal number (see example) | Segment LCD Controller | <feature type="LCD" n="1" m="16.40" name="Segment LCD Controller"/> | 1 x 16 x 40 Segment LCD Controller
Touch | Number of Touch Channels | N/A | Capacitive Touch Inputs | <feature type="Touch" n="10" name="Capacitive Touch Inputs"/> | 10 x Capacitive Touch Inputs
Other | Number of Features | N/A | Other Feature | <feature type="Other" n="2" name="My other Interface"/> | 2 x My other Interface

# /package/devices/family/.../memory

This element specifies memory regions that devices can have. Memory types are predefined and can be selected. This element can be defined on various levels. Inner memory elements supersede outer elements.

Example

</package>
...
<devices>
<family Dfamily="STM32F4" Dvendor="STMicroelectronics:13">
<memory id="IRAM1" start="0x20000000" size="0x20000" default="1"/>
<subFamily DsubFamily="STM32F407">
<debug __dp="0" __ap="0" svd="SVD\STM32F40x.svd"/>
<memory id="IRAM1" start="0x20020000" size="0x20000" default="1"/>
<memory id="IRAM2" start="0x10000000" size="0x10000" default="1"/>
<device Dname="STM32F407IE">
<memory id="IROM1" start="0x08000000" size="0x80000" startup="1" default="1"/>
</device>
</subfamily>
</family>
</devices>
...
</package>

Parents | Element Chain
--- | ---
family | /package/devices/family
subfamily | /package/devices/family/subfamily
device | /package/devices/family/../device
Attributes | Description | Type | Use
Pname | Processor identifier. This attribute is mandatory for devices that embed multiple processors. | xs:string | optional
id | Identifier of the memory region consisting of a type indicator and an index (for example, IRAM1). Predefind values can be selected as defined in MemoryIDTypeEnum. | MemoryIDTypeEnum | required
start | Base address of the memory using a hexadecimal value. | NonNegativeInteger | required
size | Size of the memory in bytes using a hexadecimal value. | NonNegativeInteger | required
default | Indicates a general purpose memory region, that does not require any special considerations (access speed, remapping, protection, etc.). If true, then an IRAM memory region will be used by the linker for locating any data and an IROM memory region will for locating any code. Every device needs at least one default IRAM region. If an algorithm element is specified (without `RAMstart` and `RAMsize` attributes), the first listed IRAM region with default="1" will also be used for executing the flash programming algorithm. Default value is false. | xs:boolean | optional
startup | If true, the startup code of the application will be placed into this memory region. Default value is false. | xs:boolean | optional

Table: Memory ID Types

The table lists identifiers for memroy types.

id= | Description
--- | ---
RAMx | External RAM. x can have a value between 1..8
ROMx | External ROM. x can have a value between 1..8
IRAMx | Internal RAM. x can have a value between 1..8
IROMx | Internal ROM. x can have a value between 1..8

# /package/devices/family/.../processor

Specifies attributes of the device processor. The element can occur on various levels. Elements of multi-processor devices can be associated with a specific processor using the attribute <Pname>. If the information is relevant to all processors, no processor must be specified in <Pname>.

Example

<package>
...
<devices>
<family Dfamily="STM32F4" Dvendor="STMicroelectronics:13">
<processor Dcore="Cortex-M4" DcoreVersion="r0p1"
Dfpu="1" Dmpu="1" Dendian="Little-endian" Dclock="168000000"/>
...
</family>
</devices>
...
</package>

Parents | Element Chain
--- | ---
family | /package/devices/family
subfamily | /package/devices/family/subfamily
device | /package/devices/family/../device
Attributes | Description | Type | Use
Pname | Processor identifier. This attribute is mandatory for devices that embed multiple processors. Each processor needs a unique identifier and must be used consistently in the Pname attribute of the elements within the scope of the current device family section. | xs:string | optional
Dvendor | Specfies the device vendor using a predefined string. Use predefined values as listed in the table Device Vendor. | DeviceVendorEnum | optional
Dcore | Specifies the processor core. Use predefined values as listed in the table Device Cores. | DcoreEnum | optional
Dfpu | Specifies whether a hardware Floating Point Unit is present in the processor. Use predefined values as listed in the table Device FPU. | DfpuEnum | optional
Dmpu | Specifies whether a Memory Protection Unit is present in the processor. Use predefined values as listed in the table Device MPU. | DmpuEnum | optional
Dendian | Specifies the endianess of the processor. Use predefined values as listed in the table Endinaness. | DendianEnum | optional
Dclock | Specifies the max clock frequency of the processor subsystem | xs:unsignedInt | optional
DcoreVersion | Hardware revision of the processor core | xs:string | required

Table: Device Vendors

The table lists predefined values representing device vendors. The list is extended from time to time (on request by new vendors). Contact cmsis.nosp@m.@arm.nosp@m..com to ask for an extension. These values can be used in the elements:

- /package/boards/board/mountedDevice
- /package/conditions/condition/accept
- /package/conditions/condition/require
- /package/conditions/condition/deny
- /package/examples/example/board
- /package/boards/board/compatibleDevice
- /package/generators/generator/select

Dvendor= | Description
--- | ---
Altera:85 | Altera: www.altera.com
Analog Devices:1 | Analog Devices: www.analog.com
ARM:82 | ARM Ltd.: www.arm.com
Atmel:3 | Atmel Corporation: www.atmel.com
Cypress:19 | Cypress Semiconductor: www.cypress.com
Engery Micro:97 | Energy Micro, now owned by Silicon Labs: www.silabs.com
Freescale Semiconductor:78 | Freescale Semiconductor: www.freescale.com
Generic:5 | Generic: Not a vendor specific device
Holtek:106 | Holtek Microelectronics: www.holtek.com
Infineon:7 | Infineon Technologies: www.infineon.com
Lapis Semiconductor:10 | Lapis Semiconductor: www.lapis-semi.com
Maxim:23 | Maxim Integrated: www.maximintegrated.com
MicroSemi:112 | Microsemi: www.microsemi.com
Milandr:99 | Milandr: www.milandr.ru
Nordic Semiconductor:54 | Nordic Semiconductor: www.nordicsemi.com
Nuvoton:18 | Nuvoton Technolgy Corp.: www.nuvoton.com
NXP:11 | NXP: www.nxp.com
Renesas:117 | Renesas: www.renesas.com
ROHM:103 | ROHM: www.rohm.com
Samsung:47 | Samsung Semiconductor: www.samsung.com
Silicon Laboratories:21 | Silicon Laboratories: www.silabs.com
Spansion:100 | Fujitsu, now Spansion: www.spansion.com
STMicroelectronics:13 | STMicroelectronics: www.st.com
Texas Instruments:16 | Texas Instruments: www.ti.com
Toshiba:92 | Toshiba Semiconductor: www.toshiba-components.com
Triad Semiconductor:104 | Triad Semiconductor: www.triadsemi.com

Table: Device Cores

The table lists available device cores. The list is extended from time to time to reflect new processor cores. These values can be used in the elements:

- /package/conditions/condition/accept
- /package/conditions/condition/require
- /package/conditions/condition/deny
- /package/devices/family/.../processor

DCore= | Description
--- | ---
Cortex-M0 | ARM Cortex-M0 processor based device
Cortex-M0+ | ARM Cortex-M0+ processor based device
Cortex-M1 | ARM Cortex-M1 processor based device
Cortex-M3 | ARM Cortex-M3 processor based device
Cortex-M4 | ARM Cortex-M4 processor based device
Cortex-M7 | ARM Cortex-M7 processor based device
SC000 | SecurCore SC000 based on technology of Cortex-M0.
SC300 | SecurCore SC300 based on technology of Cortex-M3.
Cortex-R4 | ARM Cortex-R4 processor based device
Cortex-R5 | ARM Cortex-R5 processor based device
Cortex-A8 | ARM Cortex-A8 processor based device
Cortex-A9 | ARM Cortex-A9 processor based device
Cortex-A15 | ARM Cortex-A15 processor based device
* | Device based on any processor

Table: Device FPU

The table lists values that identicate whether a CPU has an Floating Point Unit (FPU). The tokens can be used in the elements:

- /package/conditions/condition/accept
- /package/conditions/condition/require
- /package/conditions/condition/deny
- /package/devices/family/.../processor

Dfpu= | Description
--- | ---
NO_FPU | Hardware Floating Point Unit not present
FPU | Hardware Floating Point Unit present
SP_FPU | Single Precision Hardware Floating Point Unit present
DP_FPU | Double Precision Hardware Floating Point Unit present

Table: Device MPU

The table shows predefined values that identify whether a CPU has an Memory Protection Unit (MPU). The values can be used in the elements:

- /package/conditions/condition/accept
- /package/conditions/condition/require
- /package/conditions/condition/deny
- /package/devices/family/.../processor

Dmpu= | Description
--- | ---
MPU | Memory Protection Unit is present
NO_MPU | No Memory Protection Unit is present

Table: Endianness

The table lists values representing the endianness of a device. The values can be used in the elements:

- /package/conditions/condition/accept
- /package/conditions/condition/require
- /package/conditions/condition/deny
- /package/devices/family/.../processor

Dendian= | Description
--- | ---
Little-endian | The least significant byte of a multi-byte access is located at the specified address.
Big-endian | The most significant byte of a multi-byte access is located at the specified address.
Configurable | The byte ordering of multi-byte accesses is configurable.

# /package/devices/family/.../debugconfig

Default debugger configuration for a target connection.

Example

<family Dfamily="LPC4300 Series" Dvendor="NXP:11">
...
<debugconfig default="jtag" clock="10000000" swj="1"/>
...
</family>

Parents | Element Chain
--- | ---
family | /package/devices/family
subfamily | /package/devices/family/subfamily
device | /package/devices/family/../device
Attributes | Description | Type | Use
default | Specifies the default debug protocol to use for target connections. Predefined tokens must be used as defined in Table: Debug Protocol Type. Default value is swd. | DebugProtocolEnum | optional
clock | Specifies the default debug clock setting in Hz for a target connection. Default value is 10000000. | xs:unsignedInt | optional
swj | The device is accessed via a CoreSight SWJ-DP capable of switching between Serial Wire Debug (SWD) and JTAG protocols. Default value is true. | xs:bool | optional

Table: Debug Protocol Type

The table lists the values for debug protocol types.

type= | Description
--- | ---
jtag | JTAG debug protocol.
swd | ARM Serial Wire Debug (SWD) protocol.

# /package/devices/family/.../debugvars

Specify global debug access variables. Use these in addition to the pre-defined variables in order to query settings from a debug access sequences.
Define debug access variables with statements of the following form.

__var uservar = value; // Comment: Define "uservar" and initialize to "value"

Note
  - Initialization values must be constant unsigned numbers. No expressions are allowed.
  - User-defined debug access variables are read-only in a debug access sequence.
  - Pre-defined debug access variables cannot be set in this element.

Example

<family Dfamily="EFM32WG Series" Dvendor="Energy Micro:97">
...
<debugvars configfile="Debug\EFM32WGxxx.dbgconf" version="1.0">
__var __TPIU_pinlocation = 0; // Select one of four possible TPIU pin locations
__var __SWO_pinlocation = 0; // Select one of four possible SWO pin locations
</debugvars>
...
<sequences>
<sequence name="TraceStart">
...
<block if="__TPIU_pinlocation == 2">
...
<!-- Configure device to use pins as defined for TPIU pin location 2 -->
...
</block>
...
</sequence>
</sequences>
...
<debug __dp="0" __ap="0"/>
...
</family>

Parents | Element Chain
--- | ---
family | /package/devices/family
subfamily | /package/devices/family/subfamily
device | /package/devices/family/../device
Attributes | Description | Type | Use
configfile | Configuration file with path relative to the package base folder (extension *.DBGCONF). This file contains assignments of a default value to global debug access variables. This file gets copied to the project folder and is editable by the end-user. This file is read by the debugger after processing the global debug access variables. By editing the values of the debug access variables, the end-user effectively controls the behavior of sequences. The file can only assign new values but must not specify any new debug access variables. Configuration Wizard Annotations shall be used within the file to provide a graphical user interface for editing configuration options. | xs:string | optional
version | Version refers to the file version of the configfile attribute. If a configfile is specified the version attribute becomes mandatory. The version shall be incremented if any changes have been made to the global debug access variable names or default values. Based on the version information the tool environment will load a configfile with the version required by the debug description. The end-user may be required to update the settings after updating to a new version. | VersionType | optional
Pname | Reference to a processor identifier as specified for a processor element. If Pname is set for this debugvars element, the debug access variables and configfile of this element are only valid for a debug connection to the referenced processor. Otherwise, they are valid for all processors. This attribute must be set if defining multiple debugvars sections for a device. | xs:string | optional

Example: Configuration File

// File: EFM32WGxxx.dbgconf
// Version: 1.0
// <<< Use Configuration Wizard in Context Menu >>>
// <h>Trace Pin Setup
// <o> TPIU Pin Location
// <0=> Pin Location 0
// <1=> Pin Location 1
// <2=> Pin Location 2
// <3=> Pin Location 3
// <i> Select TPIU pin location for your board configuration:
// <i> - Pin Location 0 (TRACECLK: PD7, TRACEDATA0: PD6, TRACEDATA1: PD3, TRACEDATA2: PD4, TRACEDATA3: PD5)
// <i> - Pin Location 1 (TRACECLK: PF8, TRACEDATA0: PF9, TRACEDATA1: PD13, TRACEDATA2: PB15, TRACEDATA3: PF3)
// <i> - Pin Location 2 (TRACECLK: PC6, TRACEDATA0: PC7, TRACEDATA1: PD3, TRACEDATA2: PD4, TRACEDATA3: PD5)
// <i> - Pin Location 3 (TRACECLK: PA6, TRACEDATA0: PA2, TRACEDATA1: PA3, TRACEDATA2: PA4, TRACEDATA3: PA5)
// <i> Default: Pin Location 0
__TPIU_pinlocation = 0;
// <o> SWO Pin Location
// <0=> Pin Location 0
// <1=> Pin Location 1
// <2=> Pin Location 2
// <3=> Pin Location 3
// <i> Select SWO pin location for your board configuration:
// <i> - Pin Location 0 (SWO: PF2)
// <i> - Pin Location 1 (SWO: PC15)
// <i> - Pin Location 2 (SWO: PD1)
// <i> - Pin Location 3 (SWO: PD2)
// <i> Default: Pin Location 0
__SWO_pinlocation = 0;
// </h>
// <<< end of configuration section >>>

Debug Access Variables

Debug access variables hold 64-bit unsigned integer values and are used in debug access sequences to query debugger settings and states. They are read-only within a sequence except from a limited set of the pre-defined debug access variables. Use the debugvars element to specify additional user-defined debug access variables.

Table: Pre-defined Debug Access Variables
A debugger needs to support a set of pre-defined debug access variables. These are described in the following table.

Variable | Access | Description | Value=
--- | --- | --- | ---
    __protocol
| Read-Only | Debug protocol selection and parameters for target connection. | The following bit map applies: Bit 0..15: Type 0: Error 1: JTAG 2: Serial Wire Debug (SWD) Bit 16: SWJ-DP Bit 17..63: Reserved
    __connection
| Read-Only | Target connection configuration. | The following bit map applies: Bit 0..7: Connection type 0: Error or target is disconnected. 1: Connection for target debug. 2: Connection for downloading application to flash. Bit 8..15: Reset type. 0: Error. 1: Hardware Reset (debugger reset line). 2: System Reset Request. 3: Processor Reset Request ("Vector Reset"). Bit 16..63: Reserved
    __dp
| Read/Write | Debug Port selected for target accesses. This variable is initialized when entering a pre-defined debug access sequence because of a debug event. The initialization value is the __dp as defined for the used debug element. | Debug port ID as specified in a debugport element or 0 if no debugport element exists.
    __ap
| Read/Write | Access Port selected for target accesses. This variable is initialized when entering a pre-defined debug access sequence because of a debug event. The initialization value is the __ap as defined for the used debug element. | Access Port index.
    __traceout
| Read-Only | Activated trace outputs (sinks). Additionally holds information on the selected port width if a parallel trace port is enabled. | The following bit map applies: Bit 0: Serial Wire Output (SWO) Trace enabled. Bit 1: Parallel Trace Port enabled. Bit 2: Trace Buffer enabled. Bit 3..15: Reserved. Bit 16..21: Selected Parallel Trace Port size. Bit 22..63: Reserved.
    __errorcontrol
| Read/Write | Control variable for debug access error handling. All of its bit fields are intialized to 0 when entering a pre-defined debug access sequence because of a debug event. | The following bit map applies: Bit 0: Skip errors if set to 1. A debugger must continue the sequence execution. Bit 1..63: Reserved

# /package/devices/family/.../debugport

Describes a CoreSight debug port of the device and its capabilities. The element can occur on various levels. Use unique ID values for the attribute __dp to distinguish multiple debugport elements in later references.
debugport elements are required for targets with multiple debug ports. For devices with a single debug port these elements can be omitted. If no debugport element exists the only allowed __dp ID in later references is 0.

Example

<family Dfamily="LPC4300 Series" Dvendor="NXP:11">
...
<debugconfig default="jtag" clock="10000000" swj="1"/>
<debugport __dp="0">
<jtag tapindex="0"/>
<swd/>
</debugport>
<debugport __dp="1">
<jtag tapindex="1"/>
</debugport>
...
</family>

Parents | Element Chain
--- | ---
family | /package/devices/family
subfamily | /package/devices/family/subfamily
device | /package/devices/family/../device
Attributes | Description | Type | Use
__dp | Unique ID of this debugport. It must be used consistently in references within the scope of the parent section. | xs:unsignedInt | required
Child Elements | Description | Type | Occurrence
jtag | Describe JTAG Test Access Port (TAP) properties of this debug port. | JtagType | 0..1
swd | Describe CoreSight Serial Wire Debug Port (SW-DP) properties of this debug port. | SwdType | 0..1

# /package/devices/family/.../debugport/jtag

Indicates availability of a JTAG interface for the debugport parent element. Its attributes allow the manual override of a debugger's automatic JTAG Test Access Port (TAP) detection.

Example

<family Dfamily="STM32F4" Dvendor="STMicroelectronics:13">
...
<debugconfig default="swd" clock="10000000" swj="1"/>
<debugport __dp="0">
<jtag tapindex="0" idcode="0x4BA00477" irlen="4"/>
<swd idcode="0x2BA01477"/>
</debugport>
...
</family>

Parents | Element Chain
--- | ---
debugport | /package/devices/family/.../debugport
Attributes | Description | Type | Use
tapindex | Specifies the TAP index relative to the JTAG scan chain of this device. A debugger needs to determine the absolute index if the device is part of an extended scan chain. Default value is 0. | NonNegativeInteger | optional
idcode | Specifies the IDCODE of the JTAG TAP. This value overrides the IDCODE read from the target. | NonNegativeInteger | optional
irlen | Specifies the instruction register length of the JTAG TAP. This value overrides the instruction register length detected by a debugger. | xs:unsignedInt | optional

# /package/devices/family/.../debugport/swd

Indicates availability of an ARM Serial Wire Debug (SWD) interface for the debugport parent element. Its attributes allow the manual override of SWD port characteristics as read from the target and provide information for the port selection in a system with multi-drop SWD support.

Example

<family Dfamily="STM32F4" Dvendor="STMicroelectronics:13">
...
<debugconfig default="swd" clock="10000000" swj="1"/>
<debugport __dp="0">
<jtag tapindex="0" idcode="0x4BA00477" irlen="4"/>
<swd idcode="0x2BA01477"/>
</debugport>
...
</family>

Parents | Element Chain
--- | ---
debugport | /package/devices/family/.../debugport
Attributes | Description | Type | Use
idcode | Specifies the IDCODE of the SWD port. It overrides the value read from the port's IDCODE register. | NonNegativeInteger | optional

# /package/devices/family/.../sequences

Container for debug access sequences for this device.

Example

<family Dfamily="LPC4300 Series" Dvendor="NXP:11">
...
<sequences>
...
<sequence name="DebugCoreStart" Pname="Cortex-M0">
...
</sequence>
...
<sequence name="ResetSystem" Pname="Cortex-M4">
...
</sequence>
...
<sequence name="TraceStart" Pname="Cortex-M4">
...
</sequence>
...
</sequences>
...
</family>

Parents | Element Chain
--- | ---
family | /package/devices/family
subfamily | /package/devices/family/subfamily
device | /package/devices/family/../device
Child Elements | Description | Type | Occurrence
sequence | Describe a debug access sequence. | SequenceType | 1..*

# /package/devices/family/.../sequences/sequence

Describes a Debug Access Sequence which contains control and block elements. block elements contains statements including calls to Debug Access Functions. A Debug Access Sequence overrides or extends the default functionality of a development tool. Refer to Usage of Debug Access Sequences for details.

Note
  - control elements can contain other control and block elements. The maximum nesting of control elements is 10.

Example

<family Dfamily="Generic Family" Dvendor="Generic:5">
...
<sequences>
...
<sequence name="UserSequence">
<block info="Define variables and do debug accesses">
__var tpWidth = (__traceout &amp; 0x003F0000) >> 16;
...
</block>
<control if="__traceout &amp; 0x2" info="Parallel Trace Port enabled">
<block>
// Do something generic for parallel trace port trace
...
</block>
<control if="tpWidth == 1" info="Configure device for 1-bit TPIU trace.">
<block>
// Do debug accesses
...
</block>
</control>
<control if="tpWidth == 2" info="Configure device for 2-bit TPIU trace.">
<block>
// Do debug accesses
...
</block>
</control>
<control if="tpWidth == 4" info="Configure device for 4-bit TPIU trace.">
<block>
// Do debug accesses
...
</block>
</control>
</control>
...
</sequence>
...
</sequences>
...
</family>

Parents | Element Chain
--- | ---
sequences | /package/devices/family/.../sequences
Attributes | Description | Type | Use
name | Name of the Debug Access Sequence: Pre-defined names are executed by the development tool described under Usage of Debug Access Sequences. Any Debug Access Sequence can be executed the debug access function Sequence. | xs:string | required
Pname | Reference to a processor identifier as specified for a processor element. If Pname is set for this sequence element, a debugger executes the debug access sequence only for a debug connection to the referenced processor. Otherwise, it is executed for all processors. This attribute must be set if defining multiple implementations of the same debug access sequence. | xs:string | optional
disable | Disables execution of the Default Debug Access Sequence. | xs:boolean | optional
info | Descriptive text to display for example for error diagnostics. | xs:string | optional
Child Elements | Description | Type | Occurrence
control | Describe a debug access sequence flow control element. | SequenceControlType | 0..*
block | Describe a block of debug accesses. | SequenceBlockType | 0..*

Table: Pre-defined Debug Access Sequences

The following table list the Pre-defined Debug Access Sequences. For sequences that are not specified in a sequence element Default Debug Access Sequences are executed. Refer to Usage of Debug Access Sequences Usage for more information about the execution of these sequences.

name= | Description
--- | ---
DebugPortSetup | Prepare the target debug port for connection; is executed before acquiring access to the debug port. May include for example an SWJ-DP switch sequence as defined in the ARM Debug Interface (ADI) Architecture Specification. This sequence must not contain debug port/access port register and target memory accesses other than: Reading the DPIDR debug port register to release an SWD connection from its line reset. Writing the TARGETSEL debug port register (SWD protocol v2).
DebugPortStart | Connect to the target debug port and power it up; is executed after DebugPortSetup. The parent debugport is default debug port for this sequence. This sequence must not contain access port register and target memory accesses.
DebugPortStop | Power down and disconnect from target debug port. Executed as last step during target disconnect unless another debugger connection to this port is active. The parent debugport is default debug port for this sequence. This sequence must not contain access port register and target memory accesses.
DebugDeviceUnlock | Check if the device is in a locked state and unlock it. Use query command elements for user confirmation. Executed after having powered up the debug port.
DebugCoreStart | Initialize core debug system. Executed after having connected and powered up the default debug port for the connection.
DebugCoreStop | Uninitialize core debug system. Executed as last step during disconnect before powering down any debug ports no longer required for concurrent connections.
DebugCodeMemRemap | Remap memory to execution location. Executed before verifying memory content after flash programming. This is required to replicate a memory remap of a device bootloader (that is not executed during debug connection).
ResetSystem | Execute a system-wide reset via software mechanisms.
ResetProcessor | Execute a processor reset via software mechanisms.
ResetHardware | Execute a system-wide reset via the dedicated debugger reset line, e.g. nRST.
ResetHardwareAssert | Assert a system-wide reset via the dedicated debugger reset line, e.g. nRST.
ResetHardwareDeassert | Deassert a system-wide reset via the dedicated debugger reset line, e.g. nRST.
ResetCatchSet | Executed before a target reset to configure the vector catch to stop code execution after the reset. The implementation of ResetCatchSet requires an implementation of ResetCatchClear to free any hardware resources used for stopping the core.
ResetCatchClear | Executed after a target reset to free hardware resources allocated by ResetCatchSet.
FlashEraseDone | Executed after erasing flash memory.
FlashProgramDone | Eexecuted after programming flash memory.
TraceStart | Enable target trace capture. Executed before the debugger powers up and configures standard CoreSight trace components, e.g. after the initial target connection as well as after a system-wide reset.
TraceStop | Disable target trace capture. Executed after the debugger disabled and powered down standard CoreSight trace components.
RecoverySupportStart | Executed before step or run command to support recovery from a lost target connection, e.g. after a low power mode.
RecoverySupportStop | Executed after step or run command in context of the RecoverySupportStart sequence.
RecoveryAcknowledge | Debugger acknowledge after recovering from a lost target connection. Can be executed independently from a RecoverySupportStart sequence.

# /package/devices/family/.../sequences/sequence/control

Describes flow control like if and while blocks for debug access sequences.

Example

<family Dfamily="Generic Family" Dvendor="Generic:5">
...
<sequences>
...
<sequence name="UserSequence">
...
<block info="Define variables and do debug accesses">
__var doIfBlock = 1;
__var whileCondition = 1;
...
</block>
...
<control if="doIfBlock">
<block>
// Do debug accesses
...
</block>
</control>
...
<control while="whileCondition" timeout="5000">
<block>
// Execute while "whileCondition" different from '0' with a timeout of 5ms
whileCondition = 0;
</block>
</control>
...
</sequence>
...
</sequences>
...
</family>

Parents | Element Chain
--- | ---
sequence | /package/devices/family/.../sequences/sequence
control | /package/devices/family/.../sequences/sequence/control
Attribute | Description | Type | Use
if | Expression describing the condition under which to execute this sequence block. The block is skipped if the condition resolved to false. Defaults to true if not set. Refer to Expression Rules for the syntax. | ExpressionType | optional
while | Expression describing a while-condition. The execution of the block contents is repeated while the condition resolves to true, or until an optional timeout is reached. Refer to Expression Rules for the syntax. | ExpressionType | optional
timeout | Timeout in microseconds for a block with a while condition. A debugger must extend the timeout to the closest possible time granularity. If the timeout is reached, the current iteration including a last evaluation of the while condition must finish. A value of 0 disables the timeout. This attribute defaults to 0. | xs:unsignedInt | optional
info | Descriptive text to display for example for error diagnostics. | xs:string | optional
Child Elements | Description | Type | Occurrence
control | Describe a debug access sequence flow control element. | SequenceControlType | 0..*
block | Describe a block of debug accesses. | SequenceBlockType | 0..*

# /package/devices/family/.../sequences/sequence/block

Describes a block of debug accesses. See Debug Access Syntax Rules for details on the allowed syntax of the block contents.

Example

<family Dfamily="Generic Family" Dvendor="Generic:5">
...
<sequences>
...
<sequence name="UserSequence">
...
<block info="Define condition variales for later use in block elements.">
// Variable definition by __var keyword
__var doIfBlock = 1;
__var whileCondition = 1;
</block>
...
</sequence>
...
</sequences>
...
</family>

Parents | Element Chain
--- | ---
sequence | /package/devices/family/.../sequences/sequence
control | /package/devices/family/.../sequences/sequence/control
Attribute | Description | Type | Use
atomic | Instruct the debugger to execute the block contents atomically; a debugger needs to download and buffer all debug accesses to the debug probe and finish the execution without further communication to the host PC. If a debugger cannot support an atomic block it must abort the execution of the debug access sequence. | xs:boolean | optional
info | Descriptive text to display for example for error diagnostics. | xs:string | optional

Atomic Blocks:

- Do not use debug access results for subsequent accesses in the same atomic block.
- Support for atomic blocks is highly debugger dependent. Keep them as short and simple as possible to address a wide range of debuggers.
- Query and Sequence debug access functions must not be used in an atomic block.

Debug Access Syntax Rules

Debug accesses are described in block elements of a debug access sequence (sequence element). The following syntax is used for this purpose:

- The contents of a block element is a series of statements.
- Each statement must begin in a new line and is terminated by a ; character.
- A typical statement consists of variable, followed by a = character and an expression, where the = character is an assignment of the expression result to the variable:
  variable = expression;
- Alternatively, a statement can be a sole expression without storing its result to a variable.
  expression;
- Comments begin with two slashes (//) and end with a linebreak:
  // Whole line is a comment
  variable = expression; // Comment appended to statement
- Variables must be defined using the keyword __var. The definition must include an initalization of the variable:
  __var variable = 0;
- Variables can be defined only once within a scope. Scopes beging with entering a debug access sequence or a control element. They are extended to child control elements. Variables of a parent scope can be modified. Leaving a scope destroys all variables defined in it.
  block elements do not begin a new scope.
  <sequence name="MySequence">
  <block info="Block 1">
  __var condvar = 1;
  __var myvar1 = 5;
  __var myvar2 = 0;
  </block>
  <control if="condvar">
  <block>
  // __var myvar1 = 2; // Redefinition, not allowed!
  __var myvar3 = 2;
  myvar2 = myvar1 + myvar3; // Assign value (5+2) = 7
  </block>
  </control>
  <block info="Block 2">
  myvar1 = myvar2 + 1; // Variable myvar1 holds the value '8' after this statement
  // myvar2 = myvar3; // myvar3 does not exist in this scope, not allowed!
  </block>
  </sequence>
- The debug access variables __dp, __ap, and __errorcontrol can be modified within a debug access sequence. An assigned value is held until leaving the sequence. Calling another sequence by the Sequence debug access function will push their values on a sequence execution stack. The values are restored when returning from such a call.

Expression Rules

Expressions are used in various places to describe one of the following:

- A value as assigned in a debug access statement.
- A condition to use in the if attribute of a control element.
- A condition to use in the while attribute of a control element.
- A parameter to a debug access function as described below.

An expression may consist of the following:

- Constant numbers in decimal and hexadecimal representation (prefix 0x).
- Arithmetic operators such as +, -, *, /, and %.
- Bit-arithmetic operators such as &, |, ~, ^, >>, and <<.
- Comparison-operators such as ==, !=, <, >, <=, and >=.
- Logic operators such as !, &&, ||, and ==.
- Conditional expression operations like:
  (x < y) ? a : b
- Precedence of sub-expressions is indicated by brackets ((, )). C-like precedence applies if brackets are omitted.
- References to debug access variables for evaluating debug settings.
- Calls to debug access functions.

Note
  - All values used in expressions resolve to 64-bit unsigned integer values.
  - All logic-operations and comparisons resolve to the value 1 if true, to 0 otherwise.
  - XML prohibits the use of the characters &, <, and >. Use the corresponding XML entity names instead: &amp;, &lt;, and &gt;.

Table: Debug Access Functions

Debug access functions can be called in expressions in order to interact with the target device and the user. Parameters to functions can again be expressions.
By default, a debugger must abort the execution of a debug access sequence if a function call fails. However, this behavior can be controlled from a sequence by the __errorcontrol debug access variable.
The following table describes the existing debug access functions, their parameters and the debug access variables which are evaluated for the function call.

Function | Description
--- | ---
    Sequence("name")
| Execute a debug access sequence. Calling a sequence by this function causes the modifiable debug access variables __dp, __ap, and __errorcontrol to be pushed on a sequence execution stack. Returning from such a call will restore the state of these variables. Parameters: name: Name of the sequence to execute. It must be enclosed by quotes. Return Value: Always returns 0.
    Read8(addr)
| Read an 8-bit value from target memory. A device must support native 8-bit memory accesses for this function to succeed. Parameters: addr: Memory address to read from. Debug Access Variables: __dp: The debug port to use for this memory access. __ap: The access port to use for this memory access. Return Value: The 8-bit value as read from target memory.
    Read16(addr)
| Read an 16-bit value from target memory. A device must support native 16-bit memory accesses for this function to succeed. Parameters: addr: Memory address to read from. Debug Access Variables: __dp: The debug port to use for this memory access. __ap: The access port to use for this memory access. Return Value: The 16-bit value as read from target memory.
    Read32(addr)
| Read an 32-bit value from target memory. A device must support native 32-bit memory accesses for this function to succeed. Parameters: addr: Memory address to read from. Debug Access Variables: __dp: The debug port to use for this memory access. __ap: The access port to use for this memory access. Return Value: The 32-bit value as read from target memory.
    Read64(addr)
| Read an 64-bit value from target memory. A device must support native 64-bit memory accesses for this function to succeed. Parameters: addr: Memory address to read from. Debug Access Variables: __dp: The debug port to use for this memory access. __ap: The access port to use for this memory access. Return Value: The 64-bit value as read from target memory.
    ReadAP(addr)
| Read a 32-bit value from an access port register. Parameters: addr: AP register address to read from. Addresses larger than 0xF automatically cause an AP register bank switch. Debug Access Variables: __dp: The debug port to use for this memory access. __ap: The access port to use for this memory access. Return Value: The 32-bit value as read from the AP register.
    ReadDP(addr)
| Read a 32-bit value from a debug port register. Parameters: addr: DP register address to read from. Debug Access Variables: __dp: The debug port to use for this memory access. Return Value: The 32-bit value as read from the DP register.
    Write8(addr, val)
| Write an 8-bit value to target memory. A device must support native 8-bit memory accesses for this function to succeed. Parameters: addr: Memory address to write to. val: Value to write. Debug Access Variables: __dp: The debug port to use for this memory access. __ap: The access port to use for this memory access. Return Value: Always returns 0.
    Write16(addr, val)
| Write a 16-bit value to target memory. A device must support native 16-bit memory accesses for this function to succeed. Parameters: addr: Memory address to write to. val: Value to write. Debug Access Variables: __dp: The debug port to use for this memory access. __ap: The access port to use for this memory access. Return Value: Always returns 0.
    Write32(addr, val)
| Write a 32-bit value to target memory. A device must support native 32-bit memory accesses for this function to succeed. Parameters: addr: Memory address to write to. val: Value to write. Debug Access Variables: __dp: The debug port to use for this memory access. __ap: The access port to use for this memory access. Return Value: Always returns 0.
    Write64(addr, val)
| Write a 64-bit value to target memory. A device must support native 64-bit memory accesses for this function to succeed. Parameters: addr: Memory address to write to. val: Value to write. Debug Access Variables: __dp: The debug port to use for this memory access. __ap: The access port to use for this memory access. Return Value: Always returns 0.
    WriteAP(addr, val)
| Write a 32-bit value to an access port register. Addresses larger than 0xF automatically cause an AP register bank switch. Parameters: addr: Memory address to write to. val: Value to write. Debug Access Variables: __dp: The debug port to use for this memory access. __ap: The access port to use for this memory access. Return Value: Always returns 0.
    WriteDP(addr, val)
| Write a 32-bit value to a debug port register. Parameters: addr: Memory address to write to. val: Value to write. Debug Access Variables: __dp: The debug port to use for this memory access. Return Value: Always returns 0.
    DAP_Delay(delay)
| Debug probe command to wait for a specific delay. Parameters: delay: Wait time in microseconds. Return Value: Always returns 0.
    DAP_WriteABORT(value)
| Debug probe command to write an abort request to the CoreSight ABORT register of the target debug port. Parameters: value: 32-bit value to write into the CoreSight ABORT register. Debug Access Variables: __dp: The debug port to use for this memory access. Return Value: Always returns 0.
    DAP_SWJ_Pins(pinout, pinselect, pinwait)
| Debug proble command to monitor and control the I/O Pins including the nRESET device reset line. I/O Pin Mapping for pinout, pinselect, and pinwait: Bit 0: SWCLK/TCK Bit 1: SWDIO/TMS Bit 2: TDI Bit 3: TDO Bit 5: nTRST Bit 7: nRESET The pinwait time is useful in systems where the nRESET pin is implemented as open-drain output. After nRESET is de-asserted by the debugger, external circuit may still hold the target Device under reset for a time. Using the pinwait time, the debugger may monitor selected I/O Pins and wait until they the expected value appears or a timeout expires. Parameters: pinout: Value for selected output pins. pinselect: Selects which output pins will be modified. pinwait: Wait timeout for the selected output to stabilize. A debugger must extend this timeout to the closest possible time granularity. 0 = no wait 1 .. 3000000 = time in microseconds (max 3s) Return Value: The state of the I/O Pins at the end of this operation. If a debugger is not capable of monitoring the I/O Pins, it must return a value of 0xFFFFFFFF.
    DAP_SWJ_Clock(val)
| Debug probe command to set the clock frequency for JTAG and SWD communication mode. Parameters: val: Maximum SWD/JTAG Clock (SWCLK/TCK) value in Hz. Return Value: Always returns 0.
    DAP_SWJ_Sequence(cnt, val)
| Debug probe command to generate required SWJ sequences, e.g. for SWD/JTAG Reset, SWD<->JTAG switch and Dormant operation. Parameters: cnt: Number of bits in sequence: 1..64. Larger sequences need to be implemented by multiple subsequent DAP_SWJ_Sequence calls. Such a sequence of DAP_SWJ_Sequence commands must be encapsulated in an atomic block to ensure correct execution. val: Sequence generated on SWDIO/TMS (with clock @SWCLK/TCK), LSB transmitted first. Return Value: Always returns 0.
    DAP_JTAG_Sequence(cnt, tms, tdi)
| Debug probe command to generate a JTAG sequence with fixed TMS value and capture TDO. Parameters: cnt: Length of the JTAG sequence (number of TCK cycles and TDI bits): 1..64 tms: Fixed TMS value: 0..1 tdi: Data generated on TDI with one bit per TCK cycle, LSB transmitted first. Return Value: Data captured from TDO with one bit per TCK cycle, LSB captured first and padded with 0s.
    Query(type, "message", default)
| Query user input. The sequence execution stalls depending on the used type. If the debugger runs in a batch mode, this function returns the value default. Parameters: type: Query type. Can be one of: 0 : Query_Ok, displays an informative message which has to be confirmed by the user. This type allows the result OK. 1 : Query_YesNo, displays a query with the allowed results Yes and No. 2 : Query_YesNoCancel, displays a query with the allowed results Yes, No, and Cancel. 3 : Query_OkCancel, displays a query with the allowed results OK and Cancel. message: A constant string with the query message to display. It must not be an expression and it must be enclosed by quotes. default: The default value to return if the debugger runs in batch mode. See Return Values for a list of allowed values. Return Value: The result of the query. The user input maps to the following numbers: Error : 0 OK : 1 Cancel : 2 Yes : 3 No : 4

Note
  - Target memory access functions must perform a debug access of the size indicated by their name. The target system must support debug accesses of this size.
  - Results of all functions are casted to 64-bit unsigned integer values.
  - Some target access functions determine the used debug and access port by the current values of the __dp and __ap debug access variables. If a target access requires a different debug or access port than the default ones, it must change these values. This change is held until finishing the sequence the change has occurred in.

# /package/devices/family/.../debug

Describes configuration settings, default values, and patches for data accesses for a debug connection. Multiple debug elements can be defined which are either specific to a processor identified by attribute Pname, or which apply to all connections.

Example

<family Dfamily="LPC4300 Series" Dvendor="NXP:11">
...
<debug Pname="Cortex-M4" __dp="0" __ap="0" svd="SVD\LPC43xx.svd">
...
</debug>
...
<debug Pname="Cortex-M0" __dp="1" __ap="0" svd="SVD\LPC43xx.svd">
...
</debug>
...
</family>

Parents | Element Chain
--- | ---
family | /package/devices/family
subfamily | /package/devices/family/subfamily
device | /package/devices/family/../device
Attributes | Description | Type | Use
Pname | Reference to a processor identifier as specified for a processor element. If Pname is set this debug element's settings and data patches only apply for target connections to the referenced processor. Otherwise, they apply for all processors. This attribute must be set if defining multiple debug elements within the same section. | xs:string | optional
__dp | Default debug port ID to use for target accesses in this debug connection. The allowed values are defined in debugport elements for this device. If no debugport element exists, the only allowed value is 0. The debug access variable __dp is initialized to this value when entering a pre-defined debug access sequence because of a debug event. This attribute defaults to 0 if not set. | xs:unsignedInt | optional
__ap | Default access port index to use for target accesses in this debug connection. The debug access variable __ap is initialized to this value when entering a pre-defined debug access sequence because of a debug event. This attribute defaults to 0 if not set. | xs:unsignedInt | optional
svd | The system viewer description (*.SVD) file to load for this debug connection. The file path is relative to the package base folder. | xs:string | optional
Child Elements | Description | Type | Occurrence
datapatch | Define a patch to apply for data reads in this debug connection. | DataPatchType | 0..*

# /package/devices/family/.../debug/datapatch

Describes a patch a debugger shall apply when reading data from the device.

Example

<family Dfamily="LPC800 Series" Dvendor="NXP:11">
...
<debug svd="SVD\LPC800.svd">
...
<datapatch type="Mem" __ap="0" address="0x1400000C" value="0x10000000" mask="0xFFFFFFFF" info="Patch MTB BASE register"/>
...
</debug>
...
</family>

Parents | Element Chain
--- | ---
debug | /package/devices/family/.../debug
Attributes | Description | Type | Use
type | The type of data access to patch. Predefined tokens must be used as defined in Table: Data Patch Access Type. This attribute defaults to Mem if not set. | DataPatchAccessTypeEnum | optional
__dp | The debug port ID to apply the patch for. The allowed values are defined by the __dp attribute of debugport elements for this device. If no debugport element exists, the only allowed value is 0. If this attribute is not set, the debug port ID for the data patch is set to the default __dp of this debug section. | xs:unsignedInt | optional
__ap | The CoreSight access port index to apply the patch for. If this attribute is not set, the access port index for the data patch is set to the default __ap of this debug section. | xs:unsignedInt | optional
address | The address for which to apply the patch. | NonNegativeInteger | required
value | The value with which the debugger patches the data access. value is specified in little-endian format. | NonNegativeInteger | required
mask | The bits of the data access to patch. The mask value is specified in little-endian format. | NonNegativeInteger | optional
info | Descriptive text to display for example for error diagnostics. | xs:string | optional

Table: Data Patch Access Type

The table lists the allowed values for data patch access types.

type= | Description
--- | ---
DP | CoreSight Debug Port register access. Note: This type refers to accesses via the DPACC instruction for CoreSight JTAG-DPs. Please refer to the corresponding documentation for differences in the register interface between JTAG and Serial Wire debug ports.
AP | CoreSight Access Port register access.
Mem | Memory access.

# /package/devices/family/.../trace

Describes device capabilities and possible configuration settings for capturing trace. Multiple trace elements can be defined which are either specific to a processor identified by attribute Pname, or which apply to all connections.

Example

<family Dfamily="LPC4300 Series" Dvendor="NXP:11">
...
<trace Pname="Cortex-M4">
<serialwire/>
<traceport width="0x0000000B"/> <!-- support for port widths 1, 2, and 4 -->
<tracebuffer start="0x2000C000" size="0x4000"/>
</trace>
...
<trace Pname="Cortex-M0">
<!-- Empty trace section for Cortex-M0, no trace capabilities -->
</trace>
...
</family>

Parents | Element Chain
--- | ---
family | /package/devices/family
subfamily | /package/devices/family/subfamily
device | /package/devices/family/../device
Attributes | Description | Type | Use
Pname | Reference to a processor identifier as specified for a processor element. If Pname is set this trace section only applies for target connections to the referenced processor. Otherwise, it applies for all processors. This attribute must be set if defining multiple trace elements within the same section. | xs:string | optional
Child Elements | Description | Type | Occurrence
serialwire | Describe the serial wire trace output capabilities of the processor. | SerialWireType | 0..*
traceport | Describe the parallel trace port output capabilities of the processor. | TracePortType | 0..*
tracebuffer | Describe the on-device trace buffer capabilities of the processor. | TraceBufferType | 0..*

# /package/devices/family/.../trace/serialwire

Indicates serial wire trace output capabilities of the specified processor.

Example

<family Dfamily="LPC4300 Series" Dvendor="NXP:11">
...
<trace Pname="Cortex-M4">
...
<serialwire/>
...
</trace>
...
</family>

Parents | Element Chain
--- | ---
trace | /package/devices/family/.../trace

# /package/devices/family/.../trace/traceport

Indicates parallel trace port output capabilities of the specified processor. This element describes possible configuration settings for capturing trace.

Example

<family Dfamily="LPC4300 Series" Dvendor="NXP:11">
...
<trace Pname="Cortex-M4">
...
<traceport width="0x0000000B"/> <!-- support for port widths 1, 2, and 4 -->
...
</trace>
...
</family>

Parents | Element Chain
--- | ---
trace | /package/devices/family/.../trace
Attributes | Description | Type | Use
width | Parallel trace port widths supported for the processor connection (see table below). | NonNegativeInteger | optional

The attribute width specifies the available trace port width that is supported by the device. Each bit of this value represents an available trace port size. If bit n is set a trace port width of n+1 is supported. The value width=0x00008088 (as shown in the table) indicates that three port sizes (16-bit, 8-bit, and 4-bit) are supported by the device.

Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
width | 32 | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1
Value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0

# /package/devices/family/.../trace/tracebuffer

Indicates on-device trace buffer capabilities of the specified processor. This element describes possible configuration settings for capturing trace and reading it from the buffer.

Example

<family Dfamily="LPC4300 Series" Dvendor="NXP:11">
...
<trace Pname="CoreCM4">
...
<tracebuffer start="0x2000C000" size="0x4000"/>
...
</trace>
...
</family>

Parents | Element Chain
--- | ---
trace | /package/devices/family/.../trace
Attributes | Description | Type | Use
start | Start address of the on-chip memory used as trace buffer for a supported configuration. | NonNegativeInteger | optional
size | Size of the on-chip memory used as trace buffer in bytes for a supported configuration. | NonNegativeInteger | optional

# /package/devices/family/.../device/variant

Defines a device variant. The element is optional. Can exist multiple times.

Example

<device Dname="STM32F205RB">
...
<variant Dvariant="STM32F205RBT6">
<book name="doc\STM32F2_RM.PDF" title="STM32F2 Reference Manual"/>
<description>Use this device as an alternative.</description>
<feature type="QFP" count="64" name="LQFP 64 10x10x1.4" />
<feature type="Temp" n="-40" m="85" name="Industrial Temperature Range"/>
</variant>
<variant Dvariant="STM32F205RBT7">
<feature type="QFP" count="64" name="LQFP 64 10x10x1.4" />
<feature type="Temp" n="-40" m="105" name="Extended Temperature Range"/>
</variant>
...
</device>

Parents | Element Chain
--- | ---
device | /package/devices/family/../device
Attributes | Description | Type | Use
Dvariant | Name of the device variant | xs:string | required
Child Elements | Description | Type | Occurrence
book | List books that are specific to this variant. | BookType | 0..*
description | Device description. | DescriptionType | 0..*
feature | Define features for this device variant. | FeatureType | 0..*