| CMSIS-CORE Version 4.00 CMSIS-CORE support for Cortex-M processor-based devices

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Device Header File <device.h>

The Device Header File <device.h> contains the following sections that are device specific:

- Interrupt Number Definition provides interrupt numbers (IRQn) for all exceptions and interrupts of the device.
- Configuration of the Processor and Core Peripherals reflect the features of the device.
- Device Peripheral Access Layer provides definitions for the Peripheral Access to all device peripherals. It contains all data structures and the address mapping for device-specific peripherals.
- Access Functions for Peripherals (optional) provide additional helper functions for peripherals that are useful for programming of these peripherals. Access Functions may be provided as inline functions or can be extern references to a device-specific library provided by the silicon vendor.

Reference describes the standard features and functions of the Device Header File <device.h> in detail.

# Interrupt Number Definition

Device Header File <device.h> contains the enumeration IRQn_Type that defines all exceptions and interrupts of the device.

- Negative IRQn values represent processor core exceptions (internal interrupts).
- Positive IRQn values represent device-specific exceptions (external interrupts). The first device-specific interrupt has the IRQn value 0. The IRQn values needs extension to reflect the device-specific interrupt vector table in the Startup File startup_<device>.s.

Example:

The following example shows the extension of the interrupt vector table for the LPC1100 device family.

typedef enum IRQn
{
/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/
NonMaskableInt_IRQn = -14,
HardFault_IRQn = -13,
SVCall_IRQn = -5,
PendSV_IRQn = -2,
SysTick_IRQn = -1,
/****** LPC11xx/LPC11Cxx Specific Interrupt Numbers **********************************************/
WAKEUP0_IRQn = 0,
WAKEUP1_IRQn = 1,
WAKEUP2_IRQn = 2,
: :
: :
EINT1_IRQn = 30,
EINT0_IRQn = 31,
} IRQn_Type;

# Configuration of the Processor and Core Peripherals

The Device Header File <device.h> configures the Cortex-M or SecurCore processor and the core peripherals with #defines that are set prior to including the file core_<cpu>.h.

The following tables list the #defines along with the possible values for each processor core. If these #defines are missing default values are used.

core_cm0.h

#define | Value Range | Default | Description
--- | --- | --- | ---
__CM0_REV | 0x0000 | 0x0000 | Core revision number ([15:8] revision number, [7:0] patch number)
__NVIC_PRIO_BITS | 2 | 2 | Number of priority bits implemented in the NVIC (device specific)
__Vendor_SysTickConfig | 0 .. 1 | 0 | If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.

core_cm0plus.h

#define | Value Range | Default | Description
--- | --- | --- | ---
__CM0PLUS_REV | 0x0000 | 0x0000 | Core revision number ([15:8] revision number, [7:0] patch number)
__NVIC_PRIO_BITS | 2 | 2 | Number of priority bits implemented in the NVIC (device specific)
__Vendor_SysTickConfig | 0 .. 1 | 0 | If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.

core_cm3.h

#define | Value Range | Default | Description
--- | --- | --- | ---
__CM3_REV | 0x0101 | 0x0200 | 0x0200 | Core revision number ([15:8] revision number, [7:0] patch number)
__NVIC_PRIO_BITS | 2 .. 8 | 4 | Number of priority bits implemented in the NVIC (device specific)
__MPU_PRESENT | 0 .. 1 | 0 | Defines if a MPU is present or not
__Vendor_SysTickConfig | 0 .. 1 | 0 | If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.

core_cm4.h

#define | Value Range | Default | Description
--- | --- | --- | ---
__CM4_REV | 0x0000 | 0x0000 | Core revision number ([15:8] revision number, [7:0] patch number)
__NVIC_PRIO_BITS | 2 .. 8 | 4 | Number of priority bits implemented in the NVIC (device specific)
__MPU_PRESENT | 0 .. 1 | 0 | Defines if a MPU is present or not
__FPU_PRESENT | 0 .. 1 | 0 | Defines if a FPU is present or not
__Vendor_SysTickConfig | 0 .. 1 | 0 | If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.

core_cm7.h

#define | Value Range | Default | Description
--- | --- | --- | ---
__CM7_REV | 0x0000 | 0x0000 | Core revision number ([15:8] revision number, [7:0] patch number)
__MPU_PRESENT | 0 .. 1 | 0 | Defines if a MPU is present or not
__NVIC_PRIO_BITS | 2 .. 8 | 4 | Number of priority bits implemented in the NVIC (device specific)
__Vendor_SysTickConfig | 0 .. 1 | 0 | If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.
__FPU_PRESENT | 0 .. 1 | 0 | Defines if a FPU is present or not. See __FPU_DP description below.
__FPU_DP | 0 .. 1 | 0 | The combination of the defines __FPU_PRESENT and __FPU_DP determine the whether the FPU is with single or double precision as shown in the table below.
__FPU_PRESENT | __FPU_DP | Description
0 | ignored | Processor has no FPU. The value set for __FPU_DP has no influence.
1 | 0 | Processor with FPU with single precision. The file ARMCM7_SP.h has preconfigured settings for this combination.
1 | 1 | Processor with FPU with double precision. The file ARMCM7_DP.h has preconfigured settings for this combination.
__ICACHE_PRESENT | 0 .. 1 | 1 | Instruction Chache present or not
__DCACHE_PRESENT | 0 .. 1 | 1 | Data Chache present or not
__DTCM_PRESENT | 0 .. 1 | 1 | Data Tightly Coupled Memory is present or not

core_sc000.h

#define | Value Range | Default | Description
--- | --- | --- | ---
__SC000_REV | 0x0000 | 0x0000 | Core revision number ([15:8] revision number, [7:0] patch number)
__NVIC_PRIO_BITS | 2 | 2 | Number of priority bits implemented in the NVIC (device specific)
__MPU_PRESENT | 0 .. 1 | 0 | Defines if a MPU is present or not
__Vendor_SysTickConfig | 0 .. 1 | 0 | If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.

core_sc300.h

#define | Value Range | Default | Description
--- | --- | --- | ---
__SC300_REV | 0x0000 | 0x0000 | Core revision number ([15:8] revision number, [7:0] patch number)
__NVIC_PRIO_BITS | 2 .. 8 | 4 | Number of priority bits implemented in the NVIC (device specific)
__MPU_PRESENT | 0 .. 1 | 0 | Defines if a MPU is present or not
__Vendor_SysTickConfig | 0 .. 1 | 0 | If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.

Example

The following code exemplifies the configuration of the Cortex-M4 Processor and Core Peripherals.

#define __CM4_REV 0x0001 /* Core revision r0p1 */
#define __MPU_PRESENT 1 /* MPU present or not */
#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 1 /* FPU present or not */
.
.
#include <core_cm4.h> /* Cortex-M4 processor and core peripherals */

# CMSIS Version and Processor Information

Defines in the core_cpu.h file identify the version of the CMSIS-CORE and the processor used. The following shows the defines in the various core_cpu.h files that may be used in the Device Header File <device.h> to verify a minimum version or ensure that the right processor core is used.

core_cm0.h

#define __CM0_CMSIS_VERSION_MAIN (0x03) /* [31:16] CMSIS HAL main version */
#define __CM0_CMSIS_VERSION_SUB (0x00) /* [15:0] CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
__CM0_CMSIS_VERSION_SUB ) /* CMSIS HAL version number */
...
#define __CORTEX_M (0x00) /* Cortex-M Core */

core_cm0plus.h

#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /* [31:16] CMSIS HAL main version */
#define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /* [15:0] CMSIS HAL sub version */
#define __CM0PLUS_CMSIS_VERSION ((__CM0P_CMSIS_VERSION_MAIN << 16) | \
__CM0P_CMSIS_VERSION_SUB ) /* CMSIS HAL version number */
...
#define __CORTEX_M (0x00) /* Cortex-M Core */

core_cm3.h

#define __CM3_CMSIS_VERSION_MAIN (0x03) /* [31:16] CMSIS HAL main version */
#define __CM3_CMSIS_VERSION_SUB (0x00) /* [15:0] CMSIS HAL sub version */
#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
__CM3_CMSIS_VERSION_SUB ) /* CMSIS HAL version number */
...
#define __CORTEX_M (0x03) /* Cortex-M Core */

core_cm4.h

#define __CM4_CMSIS_VERSION_MAIN (0x04) /* [31:16] CMSIS HAL main version */
#define __CM4_CMSIS_VERSION_SUB (0x00) /* [15:0] CMSIS HAL sub version */
#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \
__CM4_CMSIS_VERSION_SUB ) /* CMSIS HAL version number */
...
#define __CORTEX_M (0x04) /* Cortex-M Core */

core_cm7.h

#define __CM7_CMSIS_VERSION_MAIN (0x04)
#define __CM7_CMSIS_VERSION_SUB (0x00)
#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) | \
__CM7_CMSIS_VERSION_SUB )
#define __CORTEX_M (0x07)

core_sc000.h

#define __SC000_CMSIS_VERSION_MAIN (0x04) /* [31:16] CMSIS HAL main version */
#define __SC000_CMSIS_VERSION_SUB (0x00) /* [15:0] CMSIS HAL sub version */
#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \
__SC000_CMSIS_VERSION_SUB ) /* CMSIS HAL version number */
...
#define __CORTEX_SC (000) /* Cortex secure core */

core_sc300.h

#define __SC300_CMSIS_VERSION_MAIN (0x04) /* [31:16] CMSIS HAL main version */
#define __SC300_CMSIS_VERSION_SUB (0x00) /* [15:0] CMSIS HAL sub version */
#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16) | \
__SC300_CMSIS_VERSION_SUB ) /* CMSIS HAL version number */
...
#define __CORTEX_SC (300) /* Cortex secure core */

# Device Peripheral Access Layer

The Device Header File <device.h> contains for each peripheral:

- Register Layout Typedef
- Base Address
- Access Definitions

The section Peripheral Access shows examples for peripheral definitions.

# Device.h Template File

The silicon vendor needs to extend the Device.h template file with the CMSIS features described above. In addition the Device Header File <device.h> may contain functions to access device-specific peripherals. The system_Device.h Template File which is provided as part of the CMSIS specification is shown below.

    /**************************************************************************//**
     * @file     <Device>.h
     * @brief    CMSIS Cortex-M# Core Peripheral Access Layer Header File for
     *           Device <Device>
     * @version  V3.10
     * @date     23. November 2012
     *
     * @note
     *
     ******************************************************************************/
    /* Copyright (c) 2012 ARM LIMITED

       All rights reserved.
       Redistribution and use in source and binary forms, with or without
       modification, are permitted provided that the following conditions are met:
       - Redistributions of source code must retain the above copyright
         notice, this list of conditions and the following disclaimer.
       - Redistributions in binary form must reproduce the above copyright
         notice, this list of conditions and the following disclaimer in the
         documentation and/or other materials provided with the distribution.
       - Neither the name of ARM nor the names of its contributors may be used
         to endorse or promote products derived from this software without
         specific prior written permission.
       *
       THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
       AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
       IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
       ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
       LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
       CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
       SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
       INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
       CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
       ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
       POSSIBILITY OF SUCH DAMAGE.
       ---------------------------------------------------------------------------*/

    #ifndef <Device>_H      /* ToDo: replace '<Device>' with your device name */
    #define <Device>_H

    #ifdef __cplusplus
     extern "C" {
    #endif

    /* ToDo: replace '<Device>' with your device name; add your doxyGen comment   */
    /** @addtogroup <Device>_Definitions <Device> Definitions
      This file defines all structures and symbols for <Device>:
        - registers and bitfields
        - peripheral base address
        - peripheral ID
        - Peripheral definitions
      @{
    */

    /******************************************************************************/
    /*                Processor and Core Peripherals                              */
    /******************************************************************************/
    /** @addtogroup <Device>_CMSIS Device CMSIS Definitions
      Configuration of the Cortex-M# Processor and Core Peripherals
      @{
    */

    /*
     * ==========================================================================
     * ---------- Interrupt Number Definition -----------------------------------
     * ==========================================================================
     */

    typedef enum IRQn
    {
    /******  Cortex-M# Processor Exceptions Numbers ***************************************************/

    /* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M0 device                   */
      NonMaskableInt_IRQn           = -14,      /*!<  2 Non Maskable Interrupt                        */
      HardFault_IRQn                = -13,      /*!<  3 Hard Fault Interrupt                          */
      SVCall_IRQn                   = -5,       /*!< 11 SV Call Interrupt                             */
      PendSV_IRQn                   = -2,       /*!< 14 Pend SV Interrupt                             */
      SysTick_IRQn                  = -1,       /*!< 15 System Tick Interrupt                         */

    /* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M3 / Cortex-M4 device       */
      NonMaskableInt_IRQn           = -14,      /*!<  2 Non Maskable Interrupt                        */
      MemoryManagement_IRQn         = -12,      /*!<  4 Memory Management Interrupt                   */
      BusFault_IRQn                 = -11,      /*!<  5 Bus Fault Interrupt                           */
      UsageFault_IRQn               = -10,      /*!<  6 Usage Fault Interrupt                         */
      SVCall_IRQn                   = -5,       /*!< 11 SV Call Interrupt                             */
      DebugMonitor_IRQn             = -4,       /*!< 12 Debug Monitor Interrupt                       */
      PendSV_IRQn                   = -2,       /*!< 14 Pend SV Interrupt                             */
      SysTick_IRQn                  = -1,       /*!< 15 System Tick Interrupt                         */

    /******  Device Specific Interrupt Numbers ********************************************************/
    /* ToDo: add here your device specific external interrupt numbers
             according the interrupt handlers defined in startup_Device.s
             eg.: Interrupt for Timer#1       TIM1_IRQHandler   ->   TIM1_IRQn                        */
      <DeviceInterrupt>_IRQn        = 0,        /*!< Device Interrupt                                 */
    } IRQn_Type;

    /*
     * ==========================================================================
     * ----------- Processor and Core Peripheral Section ------------------------
     * ==========================================================================
     */

    /* Configuration of the Cortex-M# Processor and Core Peripherals */
    /* ToDo: set the defines according your Device                                                    */
    /* ToDo: define the correct core revision
             __CM0_REV if your device is a CORTEX-M0 device
             __CM3_REV if your device is a CORTEX-M3 device
             __CM4_REV if your device is a CORTEX-M4 device                                           */
    #define __CM#_REV                 0x0201    /*!< Core Revision r2p1                               */
    #define __NVIC_PRIO_BITS          2         /*!< Number of Bits used for Priority Levels          */
    #define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used     */
    #define __MPU_PRESENT             0         /*!< MPU present or not                               */
    /* ToDo: define __FPU_PRESENT if your devise is a CORTEX-M4                                       */
    #define __FPU_PRESENT             0        /*!< FPU present or not                                */

    /*@}*/ /* end of group <Device>_CMSIS */

    /* ToDo: include the correct core_cm#.h file
             core_cm0.h if your device is a CORTEX-M0 device
             core_cm3.h if your device is a CORTEX-M3 device
             core_cm4.h if your device is a CORTEX-M4 device                                          */
    #include <core_cm#.h>                       /* Cortex-M# processor and core peripherals           */
    /* ToDo: include your system_<Device>.h file
             replace '<Device>' with your device name                                                 */
    #include "system_<Device>.h"                /* <Device> System  include file                      */

    /******************************************************************************/
    /*                Device Specific Peripheral registers structures             */
    /******************************************************************************/
    /** @addtogroup <Device>_Peripherals <Device> Peripherals
      <Device> Device Specific Peripheral registers structures
      @{
    */

    #if defined ( __CC_ARM   )
    #pragma anon_unions
    #endif

    /* ToDo: add here your device specific peripheral access structure typedefs
             following is an example for a timer                                  */

    /*------------- 16-bit Timer/Event Counter (TMR) -----------------------------*/
    /** @addtogroup <Device>_TMR <Device> 16-bit Timer/Event Counter (TMR)
      @{
    */
    typedef struct
    {
      __IO uint32_t EN;                         /*!< Offset: 0x0000   Timer Enable Register           */
      __IO uint32_t RUN;                        /*!< Offset: 0x0004   Timer RUN Register              */
      __IO uint32_t CR;                         /*!< Offset: 0x0008   Timer Control Register          */
      __IO uint32_t MOD;                        /*!< Offset: 0x000C   Timer Mode Register             */
           uint32_t RESERVED0[1];
      __IO uint32_t ST;                         /*!< Offset: 0x0014   Timer Status Register           */
      __IO uint32_t IM;                         /*!< Offset: 0x0018   Interrupt Mask Register         */
      __IO uint32_t UC;                         /*!< Offset: 0x001C   Timer Up Counter Register       */
      __IO uint32_t RG0                         /*!< Offset: 0x0020   Timer Register                  */
           uint32_t RESERVED1[2];
      __IO uint32_t CP;                         /*!< Offset: 0x002C   Capture register                */
    } <DeviceAbbreviation>_TMR_TypeDef;
    /*@}*/ /* end of group <Device>_TMR */

    #if defined ( __CC_ARM   )
    #pragma no_anon_unions
    #endif

    /*@}*/ /* end of group <Device>_Peripherals */

    /******************************************************************************/
    /*                         Peripheral memory map                              */
    /******************************************************************************/
    /* ToDo: add here your device peripherals base addresses
             following is an example for timer                                    */
    /** @addtogroup <Device>_MemoryMap <Device> Memory Mapping
      @{
    */

    /* Peripheral and SRAM base address */
    #define <DeviceAbbreviation>_FLASH_BASE       (0x00000000UL)                              /*!< (FLASH     ) Base Address */
    #define <DeviceAbbreviation>_SRAM_BASE        (0x20000000UL)                              /*!< (SRAM      ) Base Address */
    #define <DeviceAbbreviation>_PERIPH_BASE      (0x40000000UL)                              /*!< (Peripheral) Base Address */

    /* Peripheral memory map */
    #define <DeviceAbbreviation>TIM0_BASE         (<DeviceAbbreviation>_PERIPH_BASE)          /*!< (Timer0    ) Base Address */
    #define <DeviceAbbreviation>TIM1_BASE         (<DeviceAbbreviation>_PERIPH_BASE + 0x0800) /*!< (Timer1    ) Base Address */
    #define <DeviceAbbreviation>TIM2_BASE         (<DeviceAbbreviation>_PERIPH_BASE + 0x1000) /*!< (Timer2    ) Base Address */
    /*@}*/ /* end of group <Device>_MemoryMap */

    /******************************************************************************/
    /*                         Peripheral declaration                             */
    /******************************************************************************/
    /* ToDo: add here your device peripherals pointer definitions
             following is an example for timer                                    */

    /** @addtogroup <Device>_PeripheralDecl <Device> Peripheral Declaration
      @{
    */

    #define <DeviceAbbreviation>_TIM0        ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE)
    #define <DeviceAbbreviation>_TIM1        ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE)
    #define <DeviceAbbreviation>_TIM2        ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE)
    /*@}*/ /* end of group <Device>_PeripheralDecl */

    /*@}*/ /* end of group <Device>_Definitions */

    #ifdef __cplusplus
    }
    #endif

    #endif  /* <Device>_H */